DSP realizes EAS sweep source design

1 Introduction Electronic ArTIcle Surveillance ( EAS ) is a security anti-theft device commonly used in supermarkets. The principle is that the transmitting circuit generates a swept frequency signal of 7.8MHz~8.8MHz, which is transmitted by the near field antenna. When there is a tag near the antenna (the label is a high Q LC oscillation circuit, the resonant center frequency is 7.8MHz) The tag emits a resonant electromagnetic wave signal, which is received by the EAS receiving antenna, and after demodulation, amplification, and digitization processing, an alarm message is finally sent. The traditional frequency sweep signal generation circuit is difficult to accurately control the oscillation frequency due to the poor consistency of the discrete component parameters. The linearity of the frequency variation, the sweep width and other indicators are also strictly controlled by the performance of the component. The author uses AD company's AD9834 type DDS to realize the synthesis of frequency sweeping signals. At the same time, considering the high-speed frequency variation of the signal, the digital signal processor (DSP) needs to be used to control the AD9834. The author uses TI's TMS320VC5410 digital signal processor (hereinafter referred to as C5410). The characteristics of these devices and the circuit implementation methods are described below.
2 Introduction to TMS320VC5410 and AD9834 This design requires the C5410 to send commands and data to the AD9834 through the multi-channel buffered serial port. The AD9834 generates the sweep signal required by the EAS system. The C5410 is a new generation of low-power TMS320C5000 series fixed-point digital signal processor produced by TI. It has three high-speed, full-duplex, multi-channel buffered serial ports (McBSP), each of which can support 128 channels. Speeds up to 100Mb/s. The series provides McBSP support for a variety of serial communication methods and protocols, which can be configured according to different needs of users. The multi-channel buffered serial port operates in a master-slave mode following the SPI protocol. This mode usually has one master device and one or more slave devices. The interface includes the following four signals: serial data input (also called Master-in/out-out or MISO); serial data output (also known as master-out slave or MOSI); serial shift clock (also known as SCK); slave enable signal (also known as SS). The clock stop mode of McBSP is compatible with the SPI protocol. When the McBSP is in the clock stop mode, the transmitter and receiver are internally synchronized.

The block diagram of the AD9834 is shown in Figure 1. The DDS technology it uses is a technique that synthesizes the desired frequency directly by digital accumulation and digital-to-analog conversion using the principle of linear increase of the phase of the sinusoidal signal. The AD9834 consists primarily of a numerically controlled oscillator (NCO), a phase modulator, a sinusoidal look-up table ROM, and a 10-bit D/A converter. The numerically controlled oscillator and phase modulator are mainly composed of two frequency selection registers, one phase accumulator, two phase offset registers and one phase offset adder. The maximum operating frequency is up to 50MHz.

The frequency control word of AD9834 is obtained by equation (1)

Where 0<Δphase<228-1, fMCLK up to 50MHz, is obtained by a high-stability crystal oscillator or programmed by other devices to synchronize the various components of the entire synthesizer.

The phase control word is obtained by equation (2)

ΔP=Kx2π/4096 (2)

Where 0 is less than K and less than 227-1, changing the value of K changes the output phase value.

3 system design ideas

The conventional EAS swept signal generation circuit uses a voltage controlled oscillation integrated circuit. The frequency range of the swept frequency signal can be controlled to 8.2 MHz ± 0.5 MHz by changing the DC bias of the peripheral varactor. When using full digital frequency synthesis, due to the discontinuity of the digital signal, it is impossible to generate a continuous frequency sweep signal, and only a stepped change of the frequency sweep signal can be generated, that is, a single frequency point is increased by 4 after a period of time, Then jump to another single frequency point, therefore, if the sweep frequency of the sweep signal is 8.2MHz ± -0.5MHz, the 1MHz frequency span is equally divided into 32 frequency points, so between adjacent frequency points The frequency interval Δf = 1 MHz / 31 = 0.0323 MHz. If the sweep frequency of the frequency sweep signal is 180 Hz (ie, 5.6 ms), the time occupied by each frequency point is ΔT=5.6 ms/3l=181 pμs. The ΔT is further divided into two parts. The first part ΔT1 is the oscillation time, that is, the single frequency waveform duration; the second part ΔT2 is the delay waiting time, during which there is theoretically no waveform output. In practical applications, it is useful for the system to dynamically change the ratio of ΔT2 in ΔT to control the transmit power of the EAS. If each single frequency waveform duration (frequency oscillation time) ΔT1 = 10 μs, the delay waiting time ΔT2 = (5.6 - 0.01 x 32) / 31 = 170.3 μs for each single frequency waveform. The multi-channel buffer serial port sends only one single-frequency word for about 71μs, which can complete the transmission of control words and frequency words, and can also perform complex calculations within this time. FIG. 2 is a schematic diagram of a waveform of a 32-frequency point sweep signal completed in a 180 Hz period. Among them, each frequency point is a sine wave with a certain frequency after expansion, and the frequency range of the 32-frequency swept frequency signal in each period is stepwise change from 7.7MHz to 8.7MHz.

4 hardware design and software implementation

4.1 Hardware Design

The hardware connection scheme based on the above design idea is shown in Figure 3, including C5410, 10MHz crystal oscillator, AD9834 and filter amplifier circuit. Since the AD9834's supply voltage is selectable from 2.3V to 5.5V, the C5410's supply voltage is 3.3V. Therefore, no level shifting is required when connecting. The 10MHz crystal oscillator provides an input clock to the C5410. Initialize the C5410 to operate at 100MHz, because only then can its timer period register output a 50MHz clock signal from the TOUT pin. This clock signal is output to the MCLK pin of the AD9834 as the operating clock for the AD9834. Theoretical analysis indicates that the phase noise of the output signal depends on the phase noise of the clock signal. When the output signal frequency is constant, the higher the frequency of the input clock signal, the smaller the phase noise deterioration.

The filter amplifier circuit further filters and amplifies the sweep wave signal output by the AD9834 to filter out high-frequency signal interference and noise, and control the signal-to-noise ratio within the allowable range. Due to the clutter signal interference, the sweep signal from AD9834 contains rich high-frequency components without filtering. After processing with RC or LC passive filter circuit, a set of 8.2MHz center frequency and sweep frequency range can be obtained. A clearer sweep wave at 7.7MHz~8.7MHz. The specific implementation scheme is to first filter out the high frequency component in the swept frequency signal output by the DDS through an RC loop composed of a decoupling capacitor and a resistor, and then use a complex filter circuit with an inductor (optional) LC filter circuit), after the inductor filter, not only the load current and voltage ripple are reduced, but also the waveform is smoothed. The specific values of L and c can be obtained by f=1/(LC)1/2, where f= 8.7MHz, the filter circuit is shown in Figure 4. Since the output signal amplitude of the AD9834 is only 0.88V at the maximum, it needs to be amplified to be the source of the sweep signal. It can be realized by a high-speed operational amplifier in the system.

Since the circuit is a high speed number, analog hybrid circuit, electromagnetic compatibility performance is very important. In particular, the DSP and the DDS share a power supply, so that the working signals of the device are transmitted through the power line to form interference. It is usually necessary to filter out low frequency noise at the power supply and with large electrolytic capacitors and tantalum capacitors. A 0.01pF to 0.1pF decoupling capacitor should also be connected to the power supply pin of each device.